Field of the Invention
This invention relates generally to the field of computer processors. More particularly, the invention relates to a method and apparatus for implementing a nested predicate register.
Description of the Related Art
Computer programs consist of a set of instructions intended to be executed on a computer system to perform some useful task. Typically, programs are designed to execute certain instructions conditionally, i.e., if one or more conditions are satisfied then the conditional instructions will be executed otherwise they will not be executed. In this context, “executed” means that an instruction performs a specified operation which will result in a modification of the state of the computer system and/or result in a particular sequence of events within the computer system. In traditional computer systems, conditional execution is implemented via a branch or jump instruction well known in the art. “Predicated execution” or “predication” (sometimes referred to as “conditional execution” or “guarded execution”) is a technique whereby instructions can be executed conditionally without the need for a branch instruction.
Predicated execution is implemented by associating a “predicate” with an instruction where the predicate controls whether or not that instruction is executed. If the predicate evaluates to “true,” the instruction is executed; if the predicate evaluates to “false,” the instruction is not executed. The definition of “true” and “false” may vary with each implementation. The function by which the predicate is determined to be true or false may also vary with each implementation. For example, some embodiments may define the predicate to be a single bit where a value of one is true and a value of zero is false while alternate embodiments may define the predicate to be multiple bits with a specific function for interpreting these bits to be true or false.
By conditionally executing instructions under the control of a predicate, predication eliminates branch instructions from the computer program. This is beneficial on wide and deep pipelines where the flushes due to branch mispredictions causes several “bubbles” in the execution pipeline, giving rise to a significant loss of instruction execution opportunities. Predication improves performance by eliminating branches, and thus any associated branch mispredictions. Since branch instructions typically cause breaks in the instruction fetch mechanism, predication also improves performance by increasing the number of instructions between branches, thus increasing the effective instruction fetch bandwidth.
Predicates are typically stored in a dedicated “predicate register set.” The exact form of the predicate register set may vary with each implementation. For example, some embodiments may define a plurality of registers each containing a single predicate while alternate embodiments may define the predicates to be one or more bits in a “condition code” or “flags” register. The exact number of predicates may also vary. For example, one processor architecture may define 64 predicates while another may define only 8 predicates.